Hybrid Beamforming Transmitter Modeling for Millimeter-Wave MIMO Applications

Hybrid digital and analog beamforming is an emerging technique for high-data-rate communication at millimeter-wave (mm-wave) frequencies. Experimental evaluation of such techniques is challenging, time-consuming, and costly. This article presents a hardware-oriented modeling method for predicting the performance of an mm-wave hybrid beamforming transmitter. The proposed method considers the effect of active circuit nonlinearity as well as the coupling and mismatch in the antenna array. It also provides a comprehensive prediction of radiation patterns and far-field signal distortions. Furthermore, it predicts the antenna input active impedance, considering the effect of active circuit load-dependent characteristics. The method is experimentally verified by a 29-GHz beamforming subarray module comprising an analog beamforming integrated circuit (IC) and a 2 times 2 subarray microstrip patch antenna. The measurement results present good agreement with the predicted ones for a wide range of beam-steering angles. As a use case of the model, far-field nonlinear distortions for different antenna array configurations are studied. The demonstration shows that the variation of nonlinear distortion versus steering angle depends significantly on the array configuration and beam direction. Moreover, the results illustrate the importance of considering the joint operation of beamforming ICs, antenna array, and linearization in the design of mm-wave beamforming transmitters

A 2x6b 8GS/s 17-24GHz I/Q RF-DAC based Transmitter in 22nm FDSOI CMOS

We describe a 2 76 bit Cartesian RF IQ-modulator,\ua0implemented on 0.15mm2 in a 22nm FDSOI CMOS technology.\ua0Measurements show a 3dB bandwidth of 17–24 GHz and a\ua0saturated output power of 10.4dBm with a peak drain efficiency\ua0of 15.6%. The IQ-modulator has been verified up to 8GS/s. To\ua0the best of our knowledge, this is the highest-frequency CMOS\ua0RF IQ-modulator using sub-50%-duty-cycle LO signals, and the\ua0highest sample rate reported for >3 bit fully integrated Cartesian\ua0IQ-modulators

Modeling of Long Term Memory Effects in RF Power Amplifiers with Dynamic Parameters

This paper presents a new radio frequency power amplifier behavioral model that is capable of modeling long term memory effects. The proposed model is derived by assuming linear dependence of the parameters of a conventional model to a long term memory parameter, which enables the model to better track the signal-induced changes of the power amplifier electrical behavior. The model is experimentally tested and shows a 2-3 dB improvement compared to common behavioral models

An 11 GS/s 2 710 b 20–26 GHz Modulator using Segmented Non-Linear RF-DACs and Non-Overlapping LO signals

We present a Cartesian I/Q modulator based\ua0on dual 10-bit RF-DACs. Non-overlapping LO signals and\ua0a segmented RF-DAC architecture with scaled bit currents\ua0contribute to good linearity and allow low-complexity DPD.\ua0Unit-cell flip-flops with a balanced clock distribution enable a\ua0high sample rate. Drive slope control for data switches reduce\ua0out-of-band emissions. Implemented in 22nm FDSOI CMOS, the\ua0modulator operates up to 26GHz with a maximum sample rate\ua0of 11 GS/s. The modulator is used to demonstrate transmission of\ua0a 64QAM signal at 13.2 Gb/s, a 256QAM signal at 7.33 Gb/s, and\ua0an OFDM signal comprising four aggregated 400-MHz 64QAM\ua0channels at an EVM of 6.43 %. The results demonstrate the\ua0potential of the proposed modulator architecture for realization\ua0of ultra wideband transmitters for high performance mm-wave\ua0systems

Circulator Load Modulated Amplifier: A Non-Reciprocal Wideband and Efficient PA Architecture

A novel power amplifier (PA) architecure, the Circulator Load Modulated Amplifier (CLMA), is presented and demonstrated. Based on a 3-port non-reciprocal combiner, the CLMA is able to modulate the load of a class-B amplifier by means of controlling the amplitude and phase of a class-C amplifier. The architecture enables broadband highly-efficient operation over a reconfigurable output power control range. As a proof of concept, a narrowband prototype PA based on GaN transistors and a commercial circulator is employed to validate the CLMA concept. It exhibits peak output power of 43.1 dBm and drain efficiency of 73% at 6-dB output power control range at a center frequency of 2.09 GHz

RF PA Predistortion using Non-Linear RF-DACs

Analog and/or digital predistortion may be used to linearize power amplifiers (PAs) at the cost of additional hardware. We present a novel scheme which uses segmented non-linear RF-DACs to linearize PAs at no additional hardware cost. An expanding segmented scaling chosen at design time may be adjusted using DAC bias, allowing linearization to be adapted. Simulations demonstrate the robustness and flexibility of the approach, achieving excellent overall linearity over a large range of DAC and PA bias conditions